1. Field of the Invention
The invention relates to a circuit arrangement for controlling switching transistors of an integrated circuit and to a method for controlling switching transistors of an integrated circuit.
2. Description of the Background Art
Switching applications of switching transistors are known, for example, transistors in switching voltage regulators, in which for example just a channel resistance must be minimized simply to avoid losses. In this case, transistor sizing is used, as provided by the available area. External circuit components, e.g., coils, are used for curve shaping of a current to avoid, e.g., EMC problems (EMC: electromagnetic compatibility).
Losses in switching applications for data transmission are less interesting. This applies, e.g., in input/output circuits located in the transition region from a chip to a printed circuit board. The curve shaping in this case is also determined by the switching transistor and not solely by external components. In this regard, it is a matter of an absolute value of transistor parameters. However, parameters of switching transistors in CMOS technology vary in their properties, e.g., in the form of temperature, operating voltage, and technology variations in the range of a factor of 2 . . . 2.5. If actual parameters or an actual parameter position of the switching transistors is known, countermeasures could be taken, e.g., by varying a number of active transistors.
FIG. 16 shows an exemplary input/output circuit according to the state of the art. Circuit components that represent in part only parasitic effects of lines are shown on an electronic printed circuit board (PCB). A driver circuit T is used to drive a complex, particularly capacitive load A, which by way of example has a capacitor C as a capacitive component. In CMOS technology, this is arranged as a chip on the PCB. An input/output I/O of driver circuit T is applied at an input of the load A. Parasitic effects due to the line between these components are shown by an inductive component L2 and an ohmic resistor R2*. An operating voltage source E supplies an operating voltage PVDD-PVSS, which provides a positive PCB supply voltage PVDD compared with a base supply voltage PVSS, whereby the base supply voltage PVSS depending on the circuit can also be a negative printed PCB voltage. The load A is also applied at the PCB base supply voltage PVSS. In addition, a line from the PCB base supply voltage leads to a voltage terminal of driver circuit T. A base chip supply voltage CVSS is present at the chip of the driver circuit T, however, due to parasitic effects of the line, which by way of example are represented by an inductive component L1 and an ohmic resistor R1*. The base chip supply voltage CVSS or a corresponding negative chip supply voltage CVSS is the same on average compared with the base supply voltage PVSS, but with alternating voltage components. By means of another line, another voltage terminal of the driver circuit T is applied to the positive PCB supply voltage PVDD. A modified positive chip supply voltage CVDD is present at the driver circuit T due to parasitic effects, which are shown as an inductive component L3 and an ohmic resistor R3*.
Thus, a CMOS driver circuit T on the integrated circuit controls an external load as the exemplary capacitive load A with the capacitive component C. A housing of the integrated driver circuit T and the traces on the PCB have parasitic elements in the form of the inductive components L1-L3 and ohmic resistors R1*-R3*, as well as various coupling capacitors, which are not shown in the simplified circuit diagram.
At the start of a switching process of the driver circuit T, final stage transistors as switching transistors in an inverter circuit in the driver circuit T rapidly reach their full gate voltage, whereby a drain-source voltage of the final stage transistors corresponds to an operating voltage PVDD-PVSS of the operating voltage source E. The driver circuit T thereby supplies a current Idsat* as an output current of a driver stage. Said output current Idsat* substantially determines a time period required for recharging of the capacitance of the capacitive component C in the capacitive load A. In this regard, a current path through the final stage transistors causes interference voltages as well, however, which occur at the inductive elements or components L1-L3, and thereby also causes the excitation of forming so-called RLC resonant circuits. These are in particular the resonant circuits, which form from the input/output I/O via the second inductive component L2, the second ohmic resistor R2*, the capacitive component C, and then, on the one hand, the operating voltage source E, the third ohmic resistor R3*, and the third inductive component L3 to the positive voltage terminal of the driver circuit T and, on the other, from the capacitive component C via the first resistor R1* and the first inductive component L1 to the negative or base voltage terminal of the driver circuit T. This is also influenced by the output current Idsat*, when a speed of gate control also plays a role. After about ⅘ of the recharging, the final stage transistors, however, no longer work as the current source, but resistively, which as a parameter corresponds to a channel resistance Ron of the transistor in the triode region. It is responsible for damping of the resonant circuits, because the shown parasitic resistors R1*-R3* have very low values, which do not lead to a notable additional damping. The output current Idsat* and the channel resistance are linked together via a width/length ratio of the affected final stage transistors.
FIG. 17 shows the relationships at a moderate output current Idsat* or high channel resistance by way of example as a voltage-time diagram. Shown are a positive chip supply voltage CVDD and a base chip supply voltage CVSS, which are measured in the driver circuit, whereby the external base chip supply voltage PVSS is used as a reference point. The oscillations arising thereby are considerably dampened. A signal sig at the load A is only slightly distorted.
FIG. 18 shows a corresponding voltage-time diagram at a higher output current Idsat*, at which the disturbances are worse compared with FIG. 17. It is evident that even a slight oversizing of the driver leads to less dampened oscillations of the chip internal supply voltage CVDD or CVSS, so that the output signal no longer lacks oscillations. The peaks on the positive internal supply voltage CVDD become larger. A greater driver circuit T can Make the overall situation worse. The behavior can be much worse with still greater wrong sizing of the driver circuit T. Voltage dips in the internal positive supply voltage CVDD down to half and an up to 1.5-fold overshooting are not extreme cases.
The use of measuring circuits for measuring the parameters, e.g., according to FIG. 21, has also been tried. A control unit M varies a number of active transistors T1, T1′, T1″, etc., by means of a control signal until a bridge circuit is balanced. The bridge circuit is formed by two resistors R1°, R2°, connected in series between the base supply voltage VSS and the positive supply voltage VDD, with a node located between said resistors R1°, R2° and connected to the control device M, on the one hand, and by another series connection, between the base supply voltage VSS and the positive supply voltage VDD, having a parallel circuit of the transistors T1, T1′, T1″ and a third resistor R3° connected in series thereto; in this case, a nodal point between the third resistor R3°, on the one hand, and the transistors T1, T1′, T1″, on the other, is connected to an input of the control unit M.
A channel resistance and the output current Idsat* at the output of such transistors or such a driver circuit T can be determined by balancing of this bridge circuit by varying the number of active transistors T1, T1′, T1″ by means of the control unit M, so that the output circuit with transistors similar thereto according to FIG. 19 or 20 can be adjusted accordingly. This is also possible during operation of the circuit. The at least one control signal m, generated by the control unit M, is applied at transistors of a driver circuit T. The control unit M can have, inter alia, an analog-to-digital converter and a sequential control, optionally also filters, particularly digital filters.
It is generally disadvantageous that high values of the output current Idsat * unavoidably lead to a low channel resistance and thereby lead to underdamping. As a result, oscillations of the RLC resonant circuits distort the voltage waveform at the load, so that data transmission can be disturbed.
In addition, voltage peaks arise in the internal chip supply voltage of an integrated circuit of this type, which reduce the lifetime of the circuits. Sufficient damping of the resonances is therefore to be sought.
Problems arise as a result for dimensioning of the final stage of a driver circuit. If due to a direct design or optionally an electronic activation of a suitable number of transistors, an effective final stage width/length ratio is selected, so that with a high chip temperature, low operating voltage VDD-VSS, and slow production technology, a required transmission rate is reliably achieved, a considerable overshoot at the load A and the chip internal operating voltage or supply voltage can be observed even starting at a data rate of 50 MHz, e.g., in the opposite situation, that is, a low chip temperature, high operating voltage, and rapid production technology. The situation of a high operating voltage, rapid production technology, and high chip temperature is more likely to be relevant for the lifetime, whereby this does not greatly change the problem. If dimensioning is undertaken for this case or for the rapid case, the speed in the slow case may no longer be sufficient and the data transmission becomes faulty.
The higher the sought data rate, the more likely that the goals of transmission reliability and lifetime cannot be achieved simultaneously by static sizing of the final stage width/length ratio by the direct layout or by connectable transistors according to FIG. 19 or 20.
Various methods were used to avoid this. Thus, it is prior in the art to influence a slew rate of the transistors with use of the so-called Miller effect, whereby the needed capacitors are very large however and a prestage of the driver circuit must be able to supply more current or otherwise the circuit becomes slower. A latency period increases, i.e., a time period between a change of an input signal of the driver circuit and a start of a response at the output thereof. An alternative consideration of the output signal with feedback to a control is also risky, because parasitic feedback can become established via the very disturbed operating voltage and the entire circuit can become unstable.
In a system according to FIG. 21, it is a disadvantage that the transistors T1, T1′, T1″, etc., must be replicas of the transistors that are to be controlled, therefore, i.e., in particular replicas of the final stage transistors of a driver circuit. Only then would the values measured at the transistors T1, T1′, T1″ agree sufficiently with the values occurring at the input/output drivers of the driver circuit T. Typical input/output transistors are large, whereby a value W=20 μm is not uncommon. Such values occur in assemblies of up to 16 and more transistors. Replicas of such assemblies are accordingly large. Therefore, large currents also flow through the third resistor R3. Aging or the area requirement of the third resistor R3 therefore also become a problem.
Ultimately the power requirement of such a circuit arrangement is high when all transistors T1, T1′, T1″, etc., are activated, whereby a few 100 mA can definitely result.